The present invention relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells of the split gate type. The present invention also relates to a semiconductor memory array of floating gate memory cells of the foregoing type.
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate, especially as the memory cells are scaled down in size. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
Two major issues are often implicated as memory cell dimensions are scaled down. First, the resistance in the source line increases with smaller memory cell dimensions, and a higher resistance suppresses the desirable cell current during a read event. Second, smaller memory cell dimensions result in a lower punch-through voltage VPT between the source and the bitline junction, which limits the achievable maximum floating-gate voltage Vfg during a program event. Floating-gate voltage Vfg is achieved through voltage coupling from the source region through the coupling oxide layer that is between the source and the floating gate. In a source-side injection mechanism, a higher Vfg (and thus a higher punch-through voltage VPT) is essential for a sufficient hot carrier injection efficiency.
The present invention solves the above mentioned problems by providing a (T-shaped) source region, where a wider conductive upper portion reduces source line resistance, while a narrower lower portion in the source line facilitates smaller memory cell geometries. The memory cell architecture also facilitates the coupling of source voltage to the floating gate through an oxide on the upper portion of the floating gate, in addition to coupling through the bottom coupling oxide, which enhances the coupling coefficient between the source electrode and the floating gate.
The present invention is a self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, each memory cell having a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate. The method comprises the steps of:
a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material;
b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction, each of the first trenches having an upper portion and a lower portion wherein the upper portion has a greater width than that of the lower portion;
c) filling each of the first trenches with a conductive material to form first blocks of conductive material, wherein for each of the first blocks in each active region:
the first block includes a lower portion formed in the lower portion of the first trench that is disposed adjacent to and insulated from the first layer of conductive material, and
the first block includes an upper portion formed in the upper portion of the first trench that is disposed over and insulated from the first layer of conductive material;
d) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to and electrically connected with one of the first blocks of conductive material; and
e) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals.
In another aspect of the present invention, the method includes the steps of:
a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material;
b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction, each of the first trenches having a side wall with an indentation formed therein;
c) filling each of the first trenches with a conductive material to form first blocks of conductive material, wherein for each of the first blocks in each active region:
the first block includes a lower portion formed below the indentation of the first trench sidewall that is disposed adjacent to and insulated from the first layer of conductive material, and
the first block includes an upper portion formed above the indentation of the first trench sidewall that is disposed over and insulated from the first layer of conductive material;
d) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to and electrically connected with one of the first blocks of conductive material; and
e) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals.
In yet another aspect of the present invention, an electrically programmable and erasable memory device includes a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type with a channel region therebetween, a first insulation layer disposed over said substrate, an electrically conductive floating gate disposed over said first insulation layer and extending over a portion of the channel region and over a portion of the first region, and an electrically conductive source region disposed over and electrically connected to the first region in the substrate. The source region has a lower portion that is disposed adjacent to and insulated from the floating gate and an upper portion that is disposed over and insulated from the floating gate.
In yet one more aspect of the present invention, an array of electrically programmable and erasable memory devices includes: a substrate of semiconductor material of a first conductivity type, spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction with an active region between each pair of adjacent isolation regions, and each of the active regions includes a column of pairs of memory cells extending in the first direction. Each of the memory cell pairs includes a first region and a pair of second regions spaced apart in the substrate having a second conductivity type with channel regions formed in the substrate between the first region and the second regions, a first insulation layer disposed over said substrate including over the channel regions, a pair of electrically conductive floating gates each disposed over the first insulation layer and extending over a portion of one of the channel regions and over a portion of the first region, and an electrically conductive source region disposed over and electrically connected to the first region in the substrate. The source region has a lower portion that is disposed adjacent to and insulated from the pair of floating gates and an upper portion that is disposed over and insulated from the pair of floating gates.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.